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Editor Name: Xiao (Shawn) WANG
Designation: Senior Lecturer
University: University of California, Los Angeles
Biography: X. Shawn Wang received the B.S. degree in electrical engineering at University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2011, the M.S. degree in electrical and computer engineering at the University of California, Santa Barbara (UCSB), CA, USA, in 2013, and the Ph.D. degree in electrical and computer engineering at the University of California, Los Angeles (UCLA), CA, USA, in 2018. He is currently a senior mixed-signal engineer at Qualcomm Technologies, Incorporated. His research interests include data converters, SERDES and RFIC designs. During his PhD period, he authored and co-authored around 20 technical papers, including IEEE JSSC, TMTT, T-CASI T-CASII, RFIC, CICC, TCAD, TVLSI and etc. His recent paper “An 8.8-GS/s 8b Time-Interleaved SAR ADC with 50-dB SFDR Using Complementary Dual-Loop-Assisted Buffers in 28-nm CMOS” has been selected in 2018 RFIC Symposium best student paper finalist.